Multi-core DSP Benefits

The ability to utilize an off-the-shelf, MDSP-based, Cradle Technologies solution as a common hardware base for developing an entire line of system products has immediate time-to-market and development cost savings. This approach helps OEMs to streamline entire operations and manufacturing, enabling efficiency gains that reflect directly on revenue, gross profit margin, and operational risks.

MDSP-based solutions lower the total product costs from concept to end-of-life by streamlining all phases of the development, manufacturing, and support process. Here are some examples of how the Cradle MDSP approach can affect product support:

• The ability to shift all system functions into software enables developers to remotely upgrade significant portions of products already sold. A premium class of upgrade service can be offered using a software “pure play model” increasing revenue and gross margins on a per product basis, and can also be used as a competitive barrier, as major system upgrades no longer require a hardware change.
• The ability to integrate many if not all system functions onto a single chip reduces supply chain management issues and lowers inventory risk; simply reloading software can shift product inventory.
• One chip for many applications also enables greater economies of scale and limits component level inventory risk as devices can be seamlessly shifted from slow moving product builds to faster moving product builds with little manufacturing overhead.
• Eliminating ASIC design reduces operational costs and SoC delivery risks, both growing problems, as SoC design requires small geometries that carry high NRE and mask set charges.
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Innovators find the balance between functional richness, ease of use, low cost and meeting schedules with Cradle’s “software-only” MDSP development flexibility. This avoids the high costs and problems inherent with hardware/software co-development and the tradeoffs associated with other design options:

• Cell-based ASIC: runaway development costs, extended design schedules and complexity
• Structured ASIC: die size can be 1.5-2X the size of cell-based ASIC, making them 2-3X more expensive; supporting memory requirements is problematic; difficult to pre-define structured ASIC master slices that will be cost effective
• FPGA: high unit costs, inability to match performance-size-power dissipation characteristics
• General-purpose DSP: these solutions require up to four traditional DSPs to replace a single MDSP